Senior or Staff Verification Engineer

Location: Shanghai, China

Responsibilities:

Understanding the expected functionality ofdesigns.

Developing testing and regression plans.

Designing and developing verificationenvironment.

Running RTL, gate-level and AMSsimulations/regression.

Code/functional coverage development,analysis and closure.

Requirements:

MS in EE/CS/ME.

Minimum of 2 years’ experience.

Additional qualifications include: Good ICverification skills and basic knowledge of logic and circuit design, goodcommunication and problem solving skills.

Candidate should be familiar with as SystemVerilog, UVM verification methodology.

Candidate should be familiar with industrystandard ASIC design and verification tools and flow.

Good knowledge ddr protocol and computersystem architecture would be an added advantage.

Good knowledge of Perl and shellprogramming would be an added advantage.

Design verification experience (test plan,test bench, assertions, debugging designs, code coverage etc.).

Knowledge in ASIC/FPGA design process andverification tools.

Familiar with design and verificationlanguages (Verilog, System Verilog, SVA etc.).

Scripting and automation skills (tcl, perl,makefile etc) a plus.

Familiar with C/C++.

Knowledge of DDR protocol a plus.

Independent and self-managing.